Silver-selenide/chalcogenide glass stack for resistance variable memory

ABSTRACT

The invention is related to methods and apparatus for providing a resistance variable memory element with improved data retention and switching characteristics. According to an embodiment of the invention a resistance variable memory element is provided having at least one silver-selenide layer in between glass layers, wherein at least one of the glass layers is a chalcogenide glass, preferably having a Ge x Se 100−x  composition.

FIELD OF THE INVENTION

[0001] The invention relates to the field of random access memory (RAM)devices formed using a resistance variable material, and in particularto a resistance variable memory element formed using chalcogenide glass.

BACKGROUND OF THE INVENTION

[0002] A well known semiconductor component is semiconductor memory,such as a random access memory (RAM). RAM permits repeated read andwrite operations on memory elements. Typically, RAM devices arevolatile, in that stored data is lost once the power source isdisconnected or removed. Non-limiting examples of RAM devices includedynamic random access memory (DRAM), synchronized dynamic random accessmemory (SDRAM) and static random access memory (SRAM). In addition,DRAMS and SDRAMS also typically store data in capacitors which requireperiodic refreshing to maintain the stored data.

[0003] In recent years, the number and density of memory elements inmemory devices have been increasing. Accordingly, the size of eachelement has been shrinking, which in the case of DRAMs also shortens theelement's data holding time. Typically, a DRAM memory device relies onelement capacity for data storage and receives a refresh command in aconventional standardized cycle, about every 100 milliseconds. However,with increasing element number and density, it is becoming more and moredifficult to refresh all memory elements at least once within a refreshperiod. In addition, refresh operations consume power.

[0004] Recently resistance variable memory elements, which includesprogrammable conductor memory elements, have been investigated forsuitability as semi-volatile and non-volatile random access memoryelements. Kozicki et al. in U.S. Pat. Nos. 5,761,115; 5,896,312;5,914,893; and 6,084,796, discloses a programmable conductor memoryelement including an insulating dielectric material formed of achalcogenide glass disposed between two electrodes. A conductivematerial, such as silver, is incorporated into the dielectric material.The resistance of the dielectric material can be changed between highresistance and low resistance states. The programmable conductor memoryis normally in a high resistance state when at rest. A write operationto a low resistance state is performed by applying a voltage potentialacross the two electrodes. The mechanism by which the resistance of theelement is changed is not fully understood. In one theory suggested byKozicki et al., the conductively-doped dielectric material undergoes astructural change at a certain applied voltage with the growth of aconductive dendrite or filament between the electrodes effectivelyinterconnecting the two electrodes and setting the memory element in alow resistance state. The dendrite is thought to grow through theresistance variable material in a path of least resistance.

[0005] The low resistance state will remain intact for days or weeksafter the voltage potentials are removed. Such material can be returnedto its high resistance state by applying a reverse voltage potentialbetween the electrodes of at least the same order of magnitude as usedto write the element to the low resistance state. Again, the highlyresistive state is maintained once the voltage potential is removed.This way, such a device can function, for example, as a resistancevariable memory element having two resistance states, which can definetwo logic states.

[0006] One preferred resistance variable material comprises achalcogenide glass. A specific example is germanium-selenide(Ge_(x)Se_(100−x)) comprising silver (Ag). One method of providingsilver to the germanium-selenide composition is to initially form agermanium-selenide glass and then deposit a thin layer of silver uponthe glass, for example by sputtering, physical vapor deposition, orother known techniques in the art. The layer of silver is irradiated,preferably with electromagnetic energy at a wavelength less than 600nanometers, so that the energy passes through the silver and to thesilver/glass interface, to break a chalcogenide bond of the chalcogenidematerial such that the glass is doped or photodoped with silver. Silvermay also be provided to the glass by processing the glass with silver,as in the case of a silver-germanium-selenide glass. Another method forproviding metal to the glass is to provide a layer of silver-selenide ona germanium-selenide glass.

[0007] In accordance with the current methods of incorporating silverinto the glass, the degree and nature of the crystallinity of thechalcogenide material of the memory element has a direct bearing uponits programming characteristics. Accordingly, current processes forincorporating silver require the precise control of the amounts ofGe_(x)Se_(100−x) glass and silver, so as not to incorrectly dope theglass and improperly alter the crystallinity of the chalcogenidematerial. Current processes also require careful selection of the exactstoichiometry of the glass to ensure that silver is incorporated intothe glass while the glass backbone remains in the glass forming region.

[0008] Furthermore, during semiconductor processing and/or packaging ofa fabricated original structure that incorporates the memory element,the element undergoes thermal cycling or heat processing. Heatprocessing can result in substantial amounts of silver migrating intothe memory element uncontrollably. Too much silver incorporated into thememory element may result in faster degradation, i.e., a short life, andeventually device failure.

[0009] Accordingly, there is a need for a resistance variable memoryelement having improved memory retention and switching characteristics.There is also a need for a chalcogenide glass memory element that isresistant to silver migration during thermal processing.

BRIEF SUMMARY OF THE INVENTION

[0010] In a first embodiment, the invention provides a resistancevariable memory element and a method of forming the resistance variablememory element in which a metal containing layer is formed between afirst chalcogenide glass layer and a second glass layer. One or both ofthe glass layers may be doped with a metal and one or more metalcontaining layers may be provided between the glass layers.

[0011] In a narrower aspect of the first embodiment, the inventionprovides a memory element and a method of forming the memory element inwhich at least one layer of silver-selenide is formed between a firstchalcogenide glass layer and a second glass layer. The second glasslayer may also be a chalcogenide glass layer. The stack of layerscomprising a first chalcogenide glass, a silver-selenide layer, and asecond glass layer are formed between two conductive layers orelectrodes. In a variation of the first embodiment of the invention, thestack of layers may contain more than one silver-selenide layer betweenthe chalcogenide glass layer and the second glass layer. In anothervariation of the first embodiment, the first chalcogenide glass layermay contain multiple chalcogenide glass layers and the second glasslayer may contain multiple glass layers. Thus the stack of layers maycontain one or more silver selenide layers in serial contact with eachother formed between a multi-layered chalcogenide glass layer and amulti-layered second glass layer. In yet another variation of the firstembodiment, one or more of each of the first chalcogenide glass layersand the second glass layers may contain a metal dopant, for example, asilver dopant.

[0012] According to a second embodiment, the invention provides a memoryelement and a method of forming a memory element comprising a pluralityof alternating layers of chalcogenide glass and metal containing layers,whereby the layers start with a first chlacogenide glass layer and endwith a last chalcogenide glass layer, with the first chalcogenide glasslayer contacting a first electrode and the last chalcogenide glass layercontacting a second electrode. Thus, the plurality of alternating layersof chalcogenide glass layers and metal containing layers are stackedbetween two electrodes. The metal containing layers preferably comprisesa silver-chalcogenide, such as silver-selenide. In a variation of thesecond embodiment, the metal containing layers may each contain aplurality of metal containing layers. In another variation of the secondembodiment, the chalcogenide glass layers may each contain a pluralityof chalcogenide glass layers. In yet another variation of thisembodiment, one or more of the chalcogenide glass layers may contain ametal dopant, for example, a silver dopant.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013] These and other features and advantages of the invention will bebetter understood from the following detailed description, which isprovided in connection with the accompanying drawings.

[0014]FIG. 1 illustrates a cross-sectional view of a memory elementfabricated in accordance with a first embodiment of the invention and atan initial stage of processing.

[0015]FIG. 2 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 1.

[0016]FIG. 3 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 2.

[0017]FIG. 4 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 3.

[0018]FIG. 5 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 4.

[0019]FIG. 6 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 5.

[0020]FIG. 7 illustrates a cross-sectional view of the memory element ofFIG. 1 at a stage of processing subsequent to that shown in FIG. 6.

[0021]FIG. 8 illustrates a cross-sectional view of the memory element ofFIG. 1 in accordance with a variation of the first embodiment of theinvention at a stage of processing subsequent to that shown in FIG. 4.

[0022]FIG. 9 illustrates a cross-sectional view of a second embodimentof the memory element of the invention at a stage of processingsubsequent to that shown in FIG. 4.

[0023]FIG. 10 illustrates a cross-sectional view of a variation of thesecond embodiment of the memory element of the invention at a stage ofprocessing subsequent to that shown in FIG. 4.

[0024]FIG. 11 illustrates a computer system having a memory elementformed according to the invention.

DETAILED DESCRIPTION OF THE INVENTION

[0025] In the following detailed description, reference is made tovarious specific embodiments of the invention. These embodiments aredescribed with sufficient detail to enable those skilled in the art topractice the invention. It is to be understood that other embodimentsmay be employed, and that various structural, logical and electricalchanges may be made without departing from the spirit or scope of theinvention.

[0026] The term “substrate” used in the following description mayinclude any supporting structure including but not limited to asemiconductor substrate that has an exposed substrate surface. Asemiconductor substrate should be understood to includesilicon-on-insulator (SOI), silicon-on-sapphire (SOS), doped and undopedsemiconductors, epitaxial layers of silicon supported by a basesemiconductor foundation, and other semiconductor structures. Whenreference is made to a semiconductor substrate or wafer in the followingdescription, previous process steps may have been utilized to formregions or junctions in or over the base semiconductor or foundation.

[0027] The term “silver” is intended to include not only elementalsilver, but silver with other trace metals or in various alloyedcombinations with other metals as known in the semiconductor industry,as long as such silver alloy is conductive, and as long as the physicaland electrical properties of the silver remain unchanged.

[0028] The term “silver-selenide” is intended to include various speciesof silver-selenide, including some species which have a slight excess ordeficit of silver, for instance, Ag₂Se, Ag_(2+x)Se, and Ag_(2−x)Se.

[0029] The term “semi-volatile memory” is intended to include any memorydevice or element which is capable of maintaining its memory state afterpower is removed from the device for a prolonged period of time. Thus,semi-volatile memory devices are capable of retaining stored data afterthe power source is disconnected or removed. Accordingly, the term“semi-volatile memory” is also intended to include not onlysemi-volatile memory devices, but also non-volatile memory devices.

[0030] The term “resistance variable material” is intended to includechalcogenide glasses, and chalcogenide glasses comprising a metal, suchas silver. For instance the term “resistance variable material” includessilver doped chalcogenide glasses, silver-germanium-selenide glasses,and chalcogenide glass comprising a silver selenide layer.

[0031] The term “resistance variable memory element” is intended toinclude any memory element, including programmable conductor memoryelements, semi-volatile memory elements, and non-volatile memoryelements which exhibit a resistance change in response to an appliedvoltage.

[0032] The term “chalcogenide glass” is intended to include glasses thatcomprise an element from group VIA (or group 16) of the periodic table.Group VIA elements, also referred to as chalcogens, include sulfur (S),selenium (Se), tellurium (Te), polonium (Po), and oxygen (O).

[0033] The invention will now be explained with reference to FIGS. 1-10,which illustrate exemplary embodiments of a resistance variable memoryelement 100 in accordance with the invention. FIG. 1 depicts a portionof an insulating layer 12 formed over a semiconductor substrate 10, forexample, a silicon substrate. It should be understood that theresistance variable memory element can be formed on a variety ofsubstrate materials and not just semiconductor substrates such assilicon. For example, the insulating layer 12 may be formed on a plasticsubstrate. The insulating layer 12 may be formed by any known depositionmethods, such as sputtering by chemical vapor deposition (CVD), plasmaenhanced CVD (PECVD) or physical vapor deposition (PVD). The insulatinglayer 12 may be formed of a conventional insulating oxide, such assilicon oxide (SiO₂), a silicon nitride (Si₃N₄), or a low dielectricconstant material, among many others.

[0034] A first electrode 14 is next formed over the insulating layer 12,as also illustrated in FIG. 1. The first electrode 14 may comprise anyconductive material, for example, tungsten, nickel, tantalum, aluminum,platinum, or silver, among many others. A first dielectric layer 15 isnext formed over the first electrode 14. The first dielectric layer 15may comprise the same or different materials as those described abovewith reference to the insulating layer 12.

[0035] Referring now to FIG. 2, an opening 13 extending to the firstelectrode 14 is formed in the first dielectric layer 15. The opening 13may be formed by known methods in the art, for example, by aconventional patterning and etching process. A first chalcogenide glasslayer 17 is next formed over the first dielectric layer 15, to fill inthe opening 13, as shown in FIG. 3.

[0036] According to a first embodiment of the invention, the firstchalcogenide glass layer 17 is a germanium-selenide glass having aGe_(x)Sel_(100−x) stoichiometry. The preferred stoichiometric range isbetween about Ge₂₀Se₈₀ to about Ge₄₃Se₅₇ and is more preferably aboutGe₄₀Se₆₀. The first chalcogenide glass layer 17 preferably has athickness from about 100 Å to about 1000 Å and is more preferably 150 Å.

[0037] The first chalcogenide glass layer, acts as a glass backbone forallowing a metal containing layer, such as a silver-selenide layer, tobe directly deposited thereon. The use of a metal containing layer, suchas a silver-selenide layer, in contact with the chalcogenide glass layermakes it unnecessary to provide a metal (silver) doped chalcogenideglass, which would require photodoping of the substrate with ultravioletradiation. However, it is possible to also metal (silver) dope thechalcogenide glass layer, which is in contact with the silver-selenidelayer, as an optional variant.

[0038] The formation of the first chalcogenide glass layer 17, having astoichiometric composition in accordance with the invention may beaccomplished by any suitable method. For instance, evaporation,co-sputtering germanium and selenium in the appropriate ratios,sputtering using a germanium-selenide target having the desiredstoichiometry, or chemical vapor deposition with stoichiometric amountsof GeH₄ and SeH₂ gases (or various compositions of these gases), whichresult in a germanium-selenide film of the desired stoichiometry areexamples of methods which may be used to form the first chalcogenideglass layer 17.

[0039] Referring now to FIG. 4, a first metal containing layer 18,preferably silver-selenide, is deposited over the first chalcogenideglass layer 17. Any suitable metal containing layer may be used. Forinstance, suitable metal containing layers include silver-chalcogenidelayers. Silver sulfide, silver oxide, and silver telluride are allsuitable silver-chalcogenides that may be used in combination with anysuitable chalcogenide glass layer. A variety of processes can be used toform the silver-selenide layer 18. For instance, physical vapordeposition techniques such as evaporative deposition and sputtering maybe used. Other processes such as chemical vapor deposition,co-evaporation or depositing a layer of selenium above a layer of silverto form silver-selenide can also be used.

[0040] The layers may be any suitable thickness. The thickness of thelayers depend upon the mechanism for switching. The thickness of thelayers is such that the metal containing layer is thicker than the firstchalcogenide glass layer. The metal containing layer is also thickerthan a second glass layer, described below. More preferably, thethickness of the layers are such that a ratio of the silver-selenidelayer thickness to the first chalcogenide glass layer thickness isbetween about 5:1 and about 1:1. In other words, the thickness of thesilver-selenide layer is between about 1 to about 5 times greater thanthe thickness of the first chalcogenide glass layer. Even morepreferably, the ratio is between about 3.1:1 and about 2:1silver-selenide layer thickness to first chalcogenide glass layerthickness.

[0041] Referring now to FIG. 5 a second glass layer 20 is formed overthe first silver-selenide layer 18. The second glass layer allowsdeposition of silver above the silver-selenide layer since silver cannotbe directly deposited on silver-selenide. Also, it is believed that thesecond glass layer may prevent or regulate migration of metal, such assilver, from an electrode into the element. Accordingly, although theexact mechanism by which the second glass layer may regulate or preventmetal migration is not clearly understood, the second glass layer mayact as a silver diffusion control layer. For use as a diffusion controllayer, any suitable glass may be used, including but not limited tochalcogenide glasses. The second chalcogenide glass layer may, but neednot, have the same stoichiometric composition as the first chalcogenideglass layer, e.g., GexSe100−x. Thus, the second glass layer 20 may be ofa different material, different stoichiometry, and/or more rigid thanthe first chalcogenide glass layer 17.

[0042] The second glass layer 20, when used as a diffusion control layermay generally comprise any suitable glass material with the exception ofSiGe and GaAs. Suitable glass material compositions for the second glasslayer 20 include, SiSe (silicon-selenide), AsSe (arseic-selenide, suchas As₃Se₂), GeS (germanium-sulfide), and combinations of Ge, Ag, and Se.Any one of the suitable glass materials may further comprise smallconcentrations, i.e. less than about 3%, of dopants to include nitrides,metal, and other group 13-16 elements from the periodic table.

[0043] The thickness of the layers are such that the silver-selenidelayer thickness is greater than the thickness of the second glass layer.Preferably, a ratio of the silver-selenide layer thickness to the secondglass layer thickness is between about 5:1 and about 1:1. Morepreferably, the ratio of the silver-selenide layer thickness to thethickness of the second glass layer is between about 3.3:1 and about 2:1silver-selenide layer thickness to second glass layer thickness. Thesecond glass layer 20 preferably has a thickness between about 100 Å toabout 1000 Å and is more preferably 150 Å.

[0044] The formation of the second glass layer 20 may be accomplished byany suitable method. For instance, chemical vapor deposition,evaporation, co-sputtering, or sputtering using a target having thedesired stoichiometry, may be used.

[0045] Referring now to FIG. 6, a second conductive electrode material22 is formed over the second glass layer 20. The second conductiveelectrode material 22 may comprise any electrically conductive material,for example, tungsten, tantalum, titanium, or silver, among many others.Typically, the second conductive electrode material 22 comprises silver.Thus, advantageously, the second glass layer 20 may be chosen toconsiderably slow or prevent migration of electrically conductivemetals, such as silver, through the resistance variable memory element100.

[0046] Referring now to FIG. 7, one or more additional dielectric layers30 may be formed over the second electrode 22 and the first dielectriclayer 15 to isolate the resistance variable memory element 100 fromother structure fabrication over the substrate 10. Conventionalprocessing steps can then be carried out to electrically couple thesecond electrode 22 to various circuits of memory arrays.

[0047] In accordance with a variation of the first embodiment of theinvention, one or more layers of a metal containing material, such assilver-selenide may be deposited on the first chalcogenide glass layer17. Any number of silver-selenide layers may be used. As shown in FIG.8, an optional second silver-selenide layer 19 may be deposited on thefirst silver-selenide layer 18 subsequent to the processing step shownin FIG. 4.

[0048] The thickness of the layers is such that the total thickness ofthe combined metal containing layers, e.g. silver-selenide layers, isgreater than or equal to the thickness of the first chalcogenide glasslayer. The total thickness of the combined metal containing layers isalso greater than the thickness of a second glass layer. It is preferredthat the total thickness of the combined metal containing layers isbetween about 1 to about 5 times greater than the thickness of the firstchalcogenide glass layer and accordingly between about 1 to about 5times greater than the thickness of the second glass layer. It is evenmore preferred that the total thickness of the combined metal containinglayers is between about 2 to about 3.3 times greater than thethicknesses of the first chalcogenide glass layer and the second glasslayer.

[0049] In accordance, with yet another variation of the invention, thefirst chalcogenide glass layer may comprise one or more layers of achalcogenide glass material, such as germanium-selenide. The secondglass layer may also comprise one or more layers of a glass material.Any suitable number of layers may be used to comprise the firstchalcogenide glass layer and/or the second glass layer. However it is tobe understood that the total thickness of the metal containing layer(s)should be thicker than the total thickness of the one or more layers ofchalcogenide glass and additionally the total thickness of the metalcontaining layer(s) should be thicker than the total thickness of theone or more layers of the second glass layer. Preferably a ratio of thetotal thickness of the metal containing layer(s) to the total thicknessof the one or more layers of chalcogenide glass is between about 5:1 andabout 1:1. Also, preferably a ratio of the total thickness of the metalcontaining layer(s) to the total thickness of the one or more layers ofthe second glass is between about 5:1 and about 1:1. It is even morepreferred that the total thickness of the metal containing layer(s) isbetween about 2 to about 3.3 times greater than the total thicknesses ofthe combined one or more layers of chalcogenide glass and the totalthickness of the combined one or more layers of the second glass

[0050] In accordance with yet another variant of the invention, one ormore of the chalcogenide glass layers and second glass layers may alsobe doped with a dopant, such as a metal, preferably silver.

[0051] Referring now to FIG. 9, which shows a second embodiment of theinvention subsequent to the processing step shown in FIG. 4, the stackof layers formed between the first and second electrodes may includealternating layers of chalcogenide glass and a metal containing layersuch as a silver-selenide layer. As shown in FIG. 9, a firstchalcogenide glass layer 17 is stacked atop a first electrode 14, afirst silver-selenide layer 18 is stacked atop the first chalcogenideglass layer 17, a second chalcogenide glass layer 117 is stacked atopthe first silver-selenide layer 18, a second silver-selenide layer 118is stacked atop the second chalcogenide glass layer 117, a thirdchalcogenide glass layer 217 is stacked atop the second silver-selenidelayer 118, a third silver-selenide layer 218 is stacked atop the thirdchalcogenide glass layer 217, and a fourth chalcogenide glass layer isstacked atop the third silver-selenide layer 218. The second conductiveelectrode 22 is formed over the fourth chalcogenide glass layer.

[0052] In accordance with the second embodiment, the stack comprises atleast two metal containing layers and at least three chalcogenide glasslayers. However, it is to be understood that the stack may comprisenumerous alternating layers of chalcogenide glass and silver-selenide,so long as the alternating layers start with a first chalcogenide glasslayer and end with a last chalcogenide glass layer, with the firstchalcogenide glass layer contacting a first electrode and the lastchalcogenide glass layer contacting a second electrode. The thicknessand ratios of the alternating layers of silver-selenide and chalcogenideglass are the same as described above, in that the silver-selenidelayers are preferably thicker than connecting chalcogenide glass layers,in a ratio of between about 5:1 and about 1:1 silver-selenide layer toconnected chalcogenide glass layer, and more preferably between about3.3:1 and 2:1 silver-selenide layer to connected chalcogenide glasslayer.

[0053] In a variation of the second embodiment, one or more layers of ametal containing material, such as silver-selenide may be depositedbetween the chalcogenide glass layers. Any number of silver-selenidelayers may be used. As shown FIG. 10 at a processing step subsequent tothat shown in FIG. 4, an additional silver-selenide layer 418 may bedeposited on the first silver-selenide layer 18 and an additionalsilver-selenide layer 518 may be deposited on the third silver-selenidelayer 218.

[0054] In accordance, with yet another variation of the invention, eachof the chalcogenide glass layers may comprise one or more thinner layersof a chalcogenide glass material, such as germanium-selenide. Anysuitable number of layers may be used to comprise the chalcogenide glasslayers.

[0055] In yet another variation of the second embodiment of theinvention, one or more of the chalcogenide glass layers may also bedoped with a dopant such as a metal, preferably comprising silver.

[0056] Devices constructed according to the first embodiment of theinvention, particularly, those having a silver-selenide layer disposedbetween two chalcogenide glass layers, show improved memory retentionand write/erase performance over conventional memory devices. Thesedevices have also shown low resistance memory retention better than 1200hours at room temperature. The devices switch at pulse widths less than2 nanoseconds compared with conventional doped resistance variablememory elements that switch at about 100 nanoseconds.

[0057] Although the embodiments described above refer to the formationof only one resistance variable memory element 100, it must beunderstood that the invention contemplates the formation of any numberof such resistance variable memory elements, which can be fabricated ina memory array and operated with memory element access circuits.

[0058]FIG. 10 illustrates a typical processor-based system 400 whichincludes a memory circuit 448, for example a programmable conductor RAM,which employs resistance variable memory elements fabricated inaccordance with the invention. A processor system, such as a computersystem, generally comprises a central processing unit (CPU) 444, such asa microprocessor, a digital signal processor, or other programmabledigital logic devices, which communicates with an input/output (I/O)device 446 over a bus 452. The memory 448 communicates with the systemover bus 452 typically through a memory controller.

[0059] In the case of a computer system, the processor system mayinclude peripheral devices such as a floppy disk drive 454 and a compactdisc (CD) ROM drive 456, which also communicate with CPU 444 over thebus 452. Memory 448 is preferably constructed as an integrated circuit,which includes one or more resistance variable memory elements 100. Ifdesired, the memory 448 may be combined with the processor, for exampleCPU 444, in a single integrated circuit.

[0060] The above description and drawings are only to be consideredillustrative of exemplary embodiments which achieve the features andadvantages of the invention. Modification and substitutions to specificprocess conditions and structures can be made without departing from thespirit and scope of the invention. Accordingly, the invention is not tobe considered as being limited by the foregoing description anddrawings, but is only limited by the scope of the appended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:
 1. A resistance variable memory elementcomprising: at least one metal containing layer, at least onechalcogenide glass layer, at least one other glass layer, said metalcontaining layer being provided between said at least one chalcogenideglass layer and said at least one other glass layer.
 2. The memoryelement of claim 1 wherein said at least one chalcogenide glass layercomprises a plurality of chalcogenide glass layers.
 3. The memoryelement of claim 1 wherein said at least one other glass layer comprisesa plurality of glass layers.
 4. The memory element of claim 1 whereinsaid at least one metal containing layer comprises asilver-chalcogenide.
 5. The memory element of claim 1 wherein said atleast one metal containing layer comprises silver-selenide.
 6. Thememory element of claim 1 wherein said at least one metal containinglayer comprises silver-sulfide.
 7. The memory element of claim 1 whereinsaid at least one metal containing layer comprises silver-oxide.
 8. Thememory element of claim 1 wherein said at least one metal containinglayer comprises silver-telluride.
 9. The memory element of claim 4wherein said at least one chalcogenide glass layer comprises a materialhaving the formula Ge_(x)Se_(100−x), wherein x=20 to
 43. 10. The memoryelement of claim 4 wherein said at least one chalcogenide glass layerstoichiometry is about Ge₄₀Se₆₀.
 11. The memory element of claim 4wherein said at least one other glass layer comprises a secondchalcogenide glass layer.
 12. The memory element of claim 4 wherein saidat least one other glass layer comprises an SiSe composition.
 13. Thememory element of claim 4 wherein said at least one other glass layercomprises an AsSe composition.
 14. The memory element of claim 4 whereinsaid at least one other glass layer comprises a GeS composition.
 15. Thememory element of claim 4 wherein said at least one other glass layercomprises a combination of germanium, silver, and selenium.
 16. Thememory element of claim 1 wherein said at least one other glass layerhas a thickness between about 100 Å and about 1000 Å.
 17. The memoryelement of claim 1 wherein said at least one other glass layer has athickness of about 150 Å.
 18. The memory element of claim 1 wherein saidat least one chalcogenide glass layer has a thickness between about 100Å and about 1000 Å.
 19. The memory element of claim 1 wherein said atleast one chalcogenide glass layer has a thickness of about 150 Å. 20.The memory element of claim 1 wherein said at least one metal containinglayer has a first thickness and said at least one chalcogenide glasslayer has a second thickness whereby a thickness ratio of said firstthickness to said second thickness is between about 5:1 to about 1:1.21. The memory element of claim 1 wherein said at least one metalcontaining layer has a first thickness and said at least onechalcogenide glass layer has a second thickness whereby a thicknessratio of said first thickness to said second thickness is between about3.3:1 to about 2:1.
 22. The memory element of claim 1 wherein said atleast one metal containing layer comprises a plurality of stacked metalcontaining layers.
 23. The memory element of claim 1 wherein said atleast one other glass layer comprises at least one second chalcogenideglass layer.
 24. The memory element of claim 23 further comprisinganother metal containing layer in contact with said at least one secondchalcogenide glass layer and at least one third chalcogenide glass layerin contact with said at least one second metal containing layer.
 25. Thememory element of claim 1 wherein one or more of said at least onechalcogenide glass layers contains a metal dopant.
 26. The memoryelement of claim 25 wherein said metal dopant comprises silver.
 27. Thememory element of claim 1 wherein said at least one metal containinglayer has a first thickness and said at least one other glass layer hasa second thickness whereby a thickness ratio of said first thickness tosaid second thickness is between about 5:1 to about 1:1.
 28. The memoryelement of claim 1 wherein said at least one metal containing layer hasa first thickness and said at least one other glass layer has a secondthickness whereby a thickness ratio of said first thickness to saidsecond thickness is between about 3.3:1 to about 2:1.
 29. The resistancevariable memory element of claim 1 wherein said at least one metalcontaining layer has a thickness equal to or greater than a thickness ofeach of said at least one chalcogenide glass layer and said at least oneother glass layer.
 30. A resistance variable memory element comprising:a body, said body comprising a first glass layer in contact with atleast one silver-chalcogenide layer, said silver-chalcogenide layerbeing in contact with a second glass layer, wherein at least one of saidfirst and second glass layers is a formed of a chalcogenide glassmaterial; and a first electrode and a second electrode in respectivecontact with said first and second glass layers.
 31. The memory elementof claim 30 wherein said at least one silver-chalcogenide layercomprises silver-selenide.
 32. The memory element of claim 30 whereinsaid at least one silver-chalcogenide layer comprises silver-sulfide.33. The memory element of claim 30 wherein said at least onesilver-chalcogenide layer comprises silver-oxide.
 34. The memory elementof claim 30 wherein said at least one silver-chalcogenide layercomprises silver-telluride.
 35. The memory element of claim 30 whereinsaid chalcogenide glass material has the formula Ge_(x)Se_(100−x),wherein x=20 to
 43. 36. The memory element of claim 30 wherein saidchalcogenide glass material stoichiometry is about Ge₄₀Se₆₀.
 37. Thememory element of claim 30 wherein both said first glass layer and saidsecond glass layer comprise a chalcogenide glass material.
 38. Thememory element of claim 30 wherein at least one of said first and secondglass layers contains a metal dopant.
 39. The memory element of claim 30wherein said metal dopant comprises silver.
 40. The memory element ofclaim 30 wherein at least another of said first and second glass layerscomprises an SiSe composition.
 41. The memory element of claim 30wherein at least another of said first and second glass layers comprisesan AsSe composition.
 42. The memory element of claim 30 wherein at leastanother of said first and second glass layers comprises a GeScomposition.
 43. The memory element of claim 30 wherein at least anotherof said first and second glass layers comprises a combination ofgermanium, silver, and selenium.
 44. The memory element of claim 30wherein said silver-chalcogenide layer has a first thickness, saidsecond glass layer has a second thickness, and a thickness ratio of saidfirst thickness to said second thickness is between about 5:1 to about1:1.
 45. The memory element of claim 30 wherein said silver-chalcogenidelayer has a first thickness, said second glass layer has a secondthickness, and a thickness ratio of said first thickness to said secondthickness is between about 3.3:1 to about 2:1.
 46. The memory element ofclaim 30 wherein said silver-chalcogenide layer has a first thicknessand said first glass layer has a second thickness and a thickness ratioof said first thickness to said second thickness is between about 5:1 toabout 1:1.
 47. The memory element of claim 30 wherein saidsilver-chalcogenide layer has a first thickness, said second glass layerhas a second thickness, and a thickness ratio of said first thickness tosaid second thickness is between about 3.3:1 to about 2:1.
 48. Thememory element of claim 30 wherein said silver-chalcogenide layer has athickness greater than or equal to the thickness of each of said firstand second glass layers.
 49. The memory element of claim 30 wherein atleast one of said first and second glass layers contains a metal dopant.50. The memory element of claim 30 wherein said metal dopant comprisessilver.
 51. A memory element comprising: a first electrode; a firstglass layer comprising Ge_(x)Se_(100−x), wherein x=20 to 43 said firstglass layer being in contact with said first electrode; a first metalcontaining layer in contact with said first glass layer; a second glasslayer in contact with said first metal containing layer; and a secondelectrode in contact with said second glass layer.
 52. The memoryelement of claim 51 wherein x is about
 40. 53. The memory element ofclaim 51 wherein said first metal containing layer comprises asilver-chalcogenide.
 54. The memory element of claim 51 wherein saidfirst metal containing layer comprises silver-selenide.
 55. The memoryelement of claim 51 wherein said first metal containing layer comprisessilver-sulfide.
 56. The memory element of claim 51 wherein said firstmetal containing layer comprises silver-oxide.
 57. The memory element ofclaim 51 wherein said first metal containing layer comprisessilver-telluride.
 58. The memory element of claim 54 wherein said secondglass layer acts as a diffusion control layer to control diffusion ofcomponents from said second electrode through said metal containinglayer and said first glass layer.
 59. The memory element of claim 58wherein said second glass layer comprises an SiSe composition.
 60. Thememory element of claim 58 wherein said second glass layer comprises anAsSe composition.
 61. The memory element of claim 58 wherein said secondglass layer comprises a GeS composition.
 62. The memory element of claim58 wherein said second glass layer comprises a combination of germanium,silver, and selenium.
 63. The memory element of claim 51 wherein saidfirst metal containing layer comprises a plurality of metal containinglayers in serial contact with each other.
 64. The memory element ofclaim 51 wherein at least one of said first glass layer and said secondglass layer comprises a plurality of glass layers in serial contact witheach other.
 65. The memory element of claim 51 wherein at least one ofsaid first and second glass layers contains a metal dopant.
 66. Thememory element of claim 65 wherein said metal dopant comprises silver.67. A chalcogenide glass stack comprising: a chalcogenide glass layer;at least one metal containing layer in contact with said chalcogenideglass layer; and a diffusion control layer in contact with said metalcontaining layer for controlling diffusion of elements into saidchalcogenide glass layer.
 68. The chalcogenide glass stack of claim 67wherein said diffusion control layer is a second glass layer.
 69. Thechalcogenide glass stack of claim 67 further comprising a metalcontaining electrode in contact with said diffusion control layer andwherein said diffusion control layer slows migration of a metal fromsaid electrode into said chalcogenide glass layer.
 70. The chalcogenideglass stack of claim 67 wherein said at least one metal containing layercomprises a silver-chalcogenide.
 71. The chalcogenide glass stack ofclaim 67 wherein said at least one metal containing layer comprisessilver-selenide.
 72. The chalcogenide glass stack of claim 67 whereinsaid at least one metal containing layer comprises silver-sulfide. 73.The chalcogenide glass stack of claim 67 wherein said at least one metalcontaining layer comprises silver-oxide.
 74. The chalcogenide glassstack of claim 67 wherein said at least one metal containing layercomprises silver-telluride.
 75. The chalcogenide glass stack of claim 67wherein at least one or both of said chalcogenide glass layer and saiddiffusion control layer contains a metal dopant.
 76. The chalcogenideglass stack of claim 75 wherein said metal dopant comprises silver. 77.A memory element comprising: a first electrode; at least one firstchalcogenide glass layer in contact with said first electrode; at leastone first metal containing layer in contact with said at least one firstchalcogenide glass layer; at least one second chalcogenide glass layerin contact with said at least one first metal containing layer; at leastone second metal containing layer in contact with said at least onesecond chalcogenide glass layer; at least one third chalcogenide glasslayer in contact with said at least one second metal containing layer;and a second electrode in contact with said at least one thirdchalcogenide glass layer.
 78. The memory element of claim 77 whereinsaid metal containing layers comprise one or more silver-selenidelayers.
 79. The memory element of claim 77 wherein one or more of saidchalcogenide glass layers comprise a plurality of chalcogenide glasslayers.
 80. The memory element of claim 77 wherein one or more of saidmetal containing layers comprises a plurality of metal containinglayers.
 81. The memory element of claim 77 wherein one or more of saidchalcogenide glass layers contains a metal dopant.
 82. The memoryelement of claim 81 wherein said metal dopant comprises silver.
 83. Amethod of forming a resistance variable memory element comprising thesteps of: forming a first electrode; forming a first chalcogenide glasslayer in contact with said first electrode; forming a first metalcontaining layer in contact with said first chalcogenide glass layer;and forming a second chalcogenide glass layer in contact with said firstmetal containing layer; forming a second metal containing layer incontact with said first chalcogenide glass layer; forming a thirdchalcogenide glass layer in contact with said second metal containinglayer; and forming a second electrode in contact with said thirdchalcogenide glass layer.
 84. The method of claim 83 wherein saidchalcogenide glass layers comprise a material having the formulaGe_(x)Se_(100−x), wherein x is between about 20 to about
 43. 85. Themethod of claim 84 wherein said chalcogenide glass layers have astoichiometry of about Ge₄₀Se₆₀.
 86. The method of claim 83 wherein saidchalcogenide glass layers comprise a plurality of chalcogenide glasslayers.
 87. The method of claim 83 wherein said metal containing layerscomprise a plurality of metal containing layers.
 88. The method of claim83 wherein one or more of said chalcogenide glass layers contain a metaldopant.
 89. The method of claim 83 wherein one or more of said metalcontaining layers comprises silver-selenide.
 90. The method of claim 88wherein said metal dopant comprises silver.
 91. The method of claim 83wherein said metal containing layers have a thickness which is equal toor greater than the thickness of each of said chalcogenide glass layers.92. The method of claim 83 wherein each of said metal containing layershas a first thickness and each of said chalcogenide glass layers has asecond thickness whereby a thickness ratio of said first thickness tosaid second thickness is between about 5:1 to about 1:1.
 93. The methodof claim 92 further wherein said thickness ratio of said first thicknessto said second thickness is between about 3.3:1 to about 2:1.
 94. Amethod of forming a resistance variable memory element comprising:forming a first glass layer; forming a silver-selenide layer in contactwith said first glass layer; and forming a second glass layer in contactwith said silver-selenide layer, whereby one of said first and secondglass layers is a formed of a chalcogenide glass material.
 95. Themethod of claim 94 wherein said chalcogenide glass material has astoichiometric composition of about Ge₄₀Se₆₀.
 96. The method of claim 94wherein at least one of said glass layers contains a metal dopant. 97.The method of claim 96 wherein said metal dopant comprises silver. 98.The method of claim 94 wherein both of said first and second glasslayers comprises a chalcogenide glass material.
 99. The method of claim98 further comprising the step of forming alternating layers of saidchalcogenide glass material and said silver-selenide layer.
 100. Themethod of claim 94 wherein said layer formed of said chalcogenide glassmaterial further contains a metal dopant.
 101. The method of claim 100wherein said metal dopant comprises silver.
 102. The method of claim 94wherein another of said first and second glass layers controls diffusionof a metal ion from an electrode through said memory element.
 103. Themethod of claim 102 wherein said other glass layer comprises an SiSecomposition.
 104. The method of claim 102 wherein said other glass layercomprises an AsSe composition.
 105. The method of claim 102 wherein saidother glass layer comprises a GeS composition.
 106. The method of claim102 wherein said other glass layer comprises a combination of germanium,silver, and selenium.
 107. The method of claim 94 wherein said metalcontaining layer has a thickness which is equal to or greater than athickness of each of said first and second glass layers.
 108. The methodof claim 94 wherein said metal containing layer comprises a plurality ofsilver-selenide layers in serial contact with each other.
 109. Aprocessor-based system, comprising: a processor; and a memory circuitconnected to said processor, said memory circuit including a resistancevariable memory element comprising at least one metal containing layer,at least one chalcogenide glass layer, at least one other glass layer,said metal containing layer being provided between said at least onechalcogenide glass layer and said at least one other glass layer. 110.The system of claim 109 wherein said chalcogenide glass layer comprisesa material having the formula Ge_(x)Se_(100−x), wherein x=20 to
 43. 111.The system of claim 109 wherein said chalcogenide glass layerstoichiometry is about Ge₄₀Se₆₀.
 112. The system of claim 109 wherein atleast one of said glass layers contains a metal dopant.
 113. The systemof claim 112 wherein said metal dopant comprises silver.
 114. The systemof claim 109 wherein said other glass layer comprises a secondchalcogenide glass layer.
 115. The system of claim 114 furthercomprising another metal containing layer in contact with said at leastone second chalcogenide glass layer and at least one third chalcogenideglass layer in contact with said at least one second metal containinglayer.
 116. The system of claim 114 wherein said chalcogenide glasslayer comprises a plurality of stacked chalcogenide glass layers. 117.The system of claim 114 wherein said metal containing layer comprises aplurality of stacked metal containing layers.
 118. The system of claim115 wherein at least one of said chalcogenide glass layers comprises ametal dopant.
 119. The system of claim 109 wherein said metal containinglayer comprises silver-selenide layer.
 120. The system of claim 119wherein said other glass layer comprises an SiSe composition.
 121. Thesystem of claim 119 wherein said other glass layer comprises an AsSecomposition.
 122. The system of claim 109 wherein said other glass layercomprises a GeS composition.
 123. The system of claim 109 wherein saidother glass layer comprises a combination of germanium, silver, andselenium.
 124. The system of claim 109 wherein said other glass layer isa diffusion control layer for slowing migration of a metal ion from anelectrode connected thereto.
 125. A processor-based system, comprising:a processor; a memory circuit connected to said processor, said memorycircuit including a first electrode; at least one first chalcogenideglass layer in contact with said first electrode; at least one firstmetal containing layer in contact with said at least one firstchalcogenide glass layer; at least one second chalcogenide glass layerin contact with said at least one first metal containing layer; at leastone second metal containing layer in contact with said at least onesecond chalcogenide glass layer; at least one third chalcogenide glasslayer in contact with said at least one second metal containing layer;and a second electrode in contact with said at least one thirdchalcogenide glass layer.
 126. The system of claim 125 wherein saidmetal containing layers comprise one or more silver-selenide layers.127. The system of claim 125 wherein one or more of said chalcogenideglass layers comprise a plurality of chalcogenide glass layers.
 128. Thesystem of claim 125 wherein one or more of said metal containing layerscomprises a plurality of metal containing layers.
 129. The system ofclaim 125 wherein one or more of said chalcogenide glass layers containsa metal dopant.
 130. The system of claim 129 wherein said metal dopantcomprises silver.
 131. A memory element comprising: a first electrode; asecond electrode; and a plurality of chalcogenide glass layers and aplurality of metal containing layers between said first and secondelectrodes, whereby said plurality of chalcogenide glass layersalternate with said metal containing layers, with one of saidchalcogenide glass layers in contact with said first electrode andanother of said chalcogenide glass layers in contact with said secondelectrode.
 132. The memory element of claim 131 wherein said pluralityof metal containing layers comprises one or more silver-selenide layers.133. The memory element of claim 131 wherein one or more of saidplurality of chalcogenide glass layers comprises a plurality ofchalcogenide glass layers.
 134. The memory element of claim 131 whereinone or more of said plurality of metal containing layers comprises aplurality of metal containing layers.
 135. The memory element of claim131 wherein one or more of said plurality of chalcogenide glass layerscontains a metal dopant.
 136. The memory element of claim 135 whereinsaid metal dopant comprises silver.
 137. A method of forming aresistance variable memory element comprising: forming a firstelectrode; forming a second electrode; and forming a plurality ofchalcogenide glass layers and a plurality of metal containing layersbetween said first and second electrodes, whereby said plurality ofchalcogenide glass layers alternate with said metal containing layers,with one of said chalcogenide glass layers in contact with said firstelectrode and another of said chalcogenide glass layers in contact withsaid second electrode.
 138. The method of claim 137 wherein saidplurality of metal containing layers comprises one or moresilver-selenide layers.
 139. The method of claim 137 wherein one or moreof said plurality of chalcogenide glass layers comprises a plurality ofchalcogenide glass layers.
 140. The method of claim 137 wherein one ormore of said plurality of metal containing layers comprises a pluralityof metal containing layers.
 141. The method of claim 137 wherein one ormore of said plurality of chalcogenide glass layers contains a metaldopant.
 142. The method of claim 141 wherein said metal dopant comprisessilver.